[Chatgpt] 數位IC設計師如何用chatgpt寫出一個讀入verilog .v檔，並印出module上所有I/O的signal name的python程式

4 min readFeb 1, 2023

前言:

將IO signal name取出並存成array去做後續字串處理，對於數位IC設計流程某些自動化是很常見的方式，這邊示範一個使用chatgpt簡單的程式來做範例，會比較好知道中間遇到的錯誤。
值得探究的是發現chatgpt給的程式有不足的部份，並且修改給chatgpt命令逐步改進程式
範例目標：python 程式可讀入verilog .v檔，並逐行印出module上所有I/O的signal name。
此範例含對話過程(詠唱)紀錄及chatgpt產生的README
此程式目前無法對應verilog module不同寫法 (有趣的是這點chatgpt 的README有寫)，好比無法處理訊號含有中括號的狀況 ex.[3:0]，或是有無寫"wire" or “reg”
雖然看過許多大神範例可以一路對話chatgpt修改程式，最終不做任何人為修改可直接上線。不過我覺得做到略為修改程度就已經非常夠了，剩下我大概只要修改幾行即可應對module的不同寫法

過程快速白話文筆記:

1.我先要求產生一個AFIFO in verilog (Appendix A)

2.要求撰寫一個python程式，讀取前面結果後，將input and output signals存到一個array並逐行列印。
chatgpt結果: 給出的程式碼直接把含有input / output整行印出來

signals.append(line)

3.示範chatgpt怎麼取出signal name
chatgpt結果:程式碼正確取出signal name，不過無法處理module中含有中括號[]的情況。

    # If it does, extract the signal name from the line
    signal_name = line.split()[2].strip(",")
    # Add the signal name to the signal_names array
    signal_names.append(signal_name)

4.我試圖要chatgpt做簡單資料清洗並刪除中括號內所有內容
chatgpt結果: 只刪除了左右中括號，但沒有刪除中括號中間的內容

    line = line.replace(",", "").replace("[", "").replace("]", "")
    # Split the line into words
    words = line.split()
    # Extract the signal name from the words
    signal_name = words[2]

5.要chatgpt改用正規標準式寫replace，期望可以看到類似”s/\[.*\]//”的東西
chatgpt結果:replace改成正規標準式寫，不過依然只刪除了中括號但沒有刪除中括號中間的內容。(完整程式碼貼於 Appendix B )

  line = re.sub(r'[\[\],]', '', line)

6.請chatgpt寫README ( Appendix C )

對話過程貼於 ( Appendix D)

Appendix A — AFIFO的verilog

module async_fifo #(
  parameter WIDTH = 8,
  parameter DEPTH = 8
) (
  input wire clk,
  input wire rst,
  input wire din,
  output wire dout,
  input wire write_en,
  input wire read_en,
  output wire full,
  output wire empty
);
  
  reg [WIDTH-1:0] memory [0:DEPTH-1];
  reg [log2(DEPTH)-1:0] write_pointer, read_pointer;
  
  always @(posedge clk or posedge rst) begin
    if (rst) begin
      write_pointer <= 0;
      read_pointer <= 0;
    end else begin
      if (write_en && !full) begin
        memory[write_pointer] <= din;
        write_pointer <= write_pointer + 1;
      end
      if (read_en && !empty) begin
        dout <= memory[read_pointer];
        read_pointer <= read_pointer + 1;
      end
    end
  end
  
  assign full = write_pointer == read_pointer + DEPTH ? 1'b1 : 1'b0;
  assign empty = write_pointer == read_pointer ? 1'b1 : 1'b0;
  
endmodule

Appendix B — python source code

import re

# Open the target.v file for reading
with open("target.v", "r") as file:
  # Read the contents of the file into a string
  contents = file.read()
  
# Split the contents of the file into lines
lines = contents.split("\n")

# Initialize an empty array to store the input and output signal names
signal_names = []

# Iterate over the lines in the file
for line in lines:
  # Remove leading spaces from the line
  line = line.lstrip()
  # Check if the line starts with "input" or "output"
  if line.startswith("input") or line.startswith("output"):
    # If it does, delete the comma and anything between brackets using regex
    line = re.sub(r'[\[\],]', '', line)
    # Split the line into words
    words = line.split()
    # Extract the signal name from the words
    signal_name = words[2]
    # Add the signal name to the signal_names array
    signal_names.append(signal_name)

# Open the OUTPUT.txt file for writing
with open("OUTPUT.txt", "w") as file:
  # Write each signal name to a separate line in the file
  for signal_name in signal_names:
    file.write(signal_name + "\n")
    
# Print the signal names to the console
for signal_name in signal_names:
  print(signal_name)

Appendix C — README

Overview

This program reads a Verilog file target.v and processes its contents to extract the input and output signal names. The program removes leading spaces, deletes all commas and anything between brackets, and only preserves the lines starting with "input" or "output". The extracted signal names are then saved to an OUTPUT.txt file and also printed to the console.

Requirements

Python 3
Regex module (import re)

Usage

To run the program, simply execute the following command in your terminal:

python program.py

The program will read the target.v file, process its contents, and write the extracted signal names to the OUTPUT.txt file and print them to the console.

Limitations

The program assumes that the Verilog file target.v follows a specific format, and may not work correctly if the file has a different format. Additionally, the program only extracts input and output signal names, and does not process any other information in the file.