[Note Sharing] Verilog — Array Instantiation & Index part select

Here is a brief sharing for a little infrequent Verilog coding style — Array Instantiation & Index part select.
Both styles could be replaced by laborious coding style in Verilog by designers. Besides, index part select often goes together with “generate”.

Array Instantiation

Reference: http://www.eecs.umich.edu/courses/eecs470/OLD/w14/labs/lab6_ex/AMI.pdf

Example

module_name instance_name [top_index : bottom_index] (
.port_name(array or concatenation of signals) ...);

Index part select

Reference:
https://www.cnblogs.com/oomusou/archive/2008/07/07/1237614.html

What is the "+:" operator called in Verilog?

Example

logic [31: 0] a_vect;
logic [0 :31] b_vect;

logic [63: 0] dword;
integer sel;

a_vect[ 0 +: 8] // == a_vect[ 7 : 0]
a_vect[15 -: 8] // == a_vect[15 : 8]
b_vect[ 0 +: 8] // == b_vect[0 : 7]
b_vect[15 -: 8] // == b_vect[8 :15]

dword[8*sel +: 8] // variable part-select with fixed width